1. Field of the Invention
The subject invention generally pertains to electronic power conversion circuits, and, more specifically, to high frequency, switched mode electronic power converters. The subject matter relates to new adaptive timing circuits that achieve optimal switch turn on timing for switches in high efficiency zero voltage switching power converters.
2. Description of Related Art
Zero voltage switching (ZVS) power converters have been demonstrated to provide significant efficiency advantages over conventional hard switching power converters, particularly for off line power supplies. The ZVS power converters eliminate drain circuit switching losses and some of the gate circuit switching losses, they eliminate rectifier reverse recovery effects, and, when the die sizes of the switches are optimized for minimum power loss they also achieve significant reductions in channel conduction losses.
In order to achieve the maximum benefit of zero voltage switching it is important to optimally time the zero voltage turn on transition. The problem is illustrated in FIG. 1. The nature of the drain source voltage transition is dependent on the drain circuit current and the available stored drain circuit energy at the beginning of the transition, as illustrated in FIG. 1. The nature of the drain source voltage transition is also dependent on the amount of voltage swing. Ideally there would always be sufficient drain circuit energy to drive the drain source voltage to zero volts and the switch would be enabled at the instant that the drain source voltage reaches zero volts. In practice, the time needed to complete the transition to zero volts varies greatly and, in some cases, there may be insufficient energy available in the drain circuit to drive the drain source voltage to zero volts. For a transition in which the drain source voltage is driven to zero volts we want to enable the switch at the instant that the drain source voltage reaches zero. If the switch is turned on after the drain source voltage reaches zero volts then there will be a period of time in which the body diode of the switch conducts and there is also the possibility that the drain circuit current will reverse and increase the drain source voltage above zero before the switch is turned on. If the body diode is allowed to conduct then there will be additional forward voltage conduction losses associated with body diode conduction, as well as reverse recovery effects which will keep the body diode in a low impedance state for a time whether or not the body diode is reverse biased. Many ZVS circuits use a fixed delay time for turn on timing of the main switch. If the fixed delay time is optimal for the condition in which there is ample sufficient energy to drive the transition to zero volts then for the condition in which there is only adequate energy to drive the transition to zero volts the turn on timing may be premature and result in considerable turn on switching losses, as illustrated in FIG. 1. We can solve the problem by using a circuit that detects the drain source voltage and turns on the switch when its drain source voltage reaches zero volts. An example of a circuit that accomplishes optimal turn on timing for the case in which there is sufficient energy to drive the drain source voltage to zero volts is illustrated in FIG. 2 and is the subject of U.S. Pat. No. 6,580,255. The FIG. 2 circuit relies on a drain connected diode to pull the gate of a P channel mosfet low in order to enable the gate of a N channel power mosfet switch as its drain source voltage reaches zero volts.
For the case in which there is insufficient energy to drive the drain source voltage to zero the adaptive timing circuit illustrated in FIG. 2 is inadequate by itself. If the drain diode in FIG. 2 is not forward biased because the drain source voltage does not reach zero then the switch will not turn on. If a mechanism is employed that results in a maximum delay time before the switch turns on then, if the maximum delay time is equal to the time that it takes for the drain source voltage to reach its minimum, then large switching losses can be avoided, however, the time that it will take for the drain to reach a minimum is highly variable and depends on both the amount of drain circuit energy available and the off state voltage of the switch. U.S. Pat. No. 6,580,255 also reveals a circuit that can sense the minimum drain voltage and enable the switch at its minimum voltage. This circuit together with the FIG. 2 circuit is illustrated in FIG. 3. The operation of the FIG. 3 circuit is illustrated in FIG. 4 where the main switch is turned on optimally for both the sufficient energy condition and the insufficient energy condition. For the insufficient energy condition the drain connected capacitor CINSUF forward biases the base emitter junction of a NPN bipolar transistor QINSUF when the drain source voltage reaches a minimum and begins to reverse direction. When QINSUF turns on then the gate of a P channel mosfet MINSUF is enabled which allows charge to flow to the gate of the power mosfet main switch before its drain source voltage can rise up significantly, thereby minimizing turn on transition switching losses in MMAIN. Most of the components of the FIG. 3 circuit can be accomplished with a low voltage application specific integrated circuit (ASIC) with the exception of the drain diode, indicated as DDRAIN in FIG. 2 and the capacitor CINSUF, illustrated in FIG. 3. It would be beneficial to reduce the number of or eliminate the components that cannot be implemented in a low voltage ASIC.